We are extremely space and power constrained. The entire discussion about PLX, Skylake-SP mesh, …., has become completely irrelevant for the GPU compute crowd.
That is important for customer buy-in. Until we learn more, we are not going to assume this is a mainstream product.Gen1 v. Gen2 EPYC is not just about the 7nm x86 chiplets. The availabilitiy to begin indexing is a internal benchmark, and we’re required to be dumb about the data structure.
Uf I said that we develop a glorified image metadata and picture editor (the kind who chooses the portrait for the front cover of SI, eg) solution, I guess I would not be too wrong to imagine the reader blinking and preparing to type in something like, “I suppose your app is emulating the last decent System 7 version of ACDSee, in WebASM, Electron and you ported that java object database, with binary emulations in case it crashes upon indexes containing the words, “run, one, anywhere, and write”. All of the system vendors that we talk to know that Rome is going to be big. This imho is a nonsense comment: Even prosumer Nvidia cards (upcoming Titan RTX) provide 100GB/sec GPU-GPU bidirectional communication.
Enough is changing, I myself have been feeling that it’s a new fresh start over. Although i am more interested to find out how it will impact the frequency of those chiplets..actual cores… since IO is out into another chip….cores might be able to Turbo better..or even have higher base frequency.“Ability to connect GPUs and do inter-GPU communication over the I/O chip and Infinity Fabric protocol so that one does not need PCIe switches or NVLink switches for chips on the same CPU. This I/O chip will handle DDR4, Infinity Fabric, PCIe and other I/O 6. These new processors are the parts of ROME family and currently being sampled to consumers.
They are also adding PCIe Gen4. Beyond that, AMD still needs to sell chips. Each x86 chiplet up to 8 cores 3.
There is a 14nm I/O chip in the middle of each package 5. Furthermore, I see nothing compelling for the HPC crowd either, nothing in the Rome setup pleases the requirements of HPC. But we have, from one view, the great niche market storage converged infrastructure application, if only the storage world didn’t pass over the big cache, high clock and low core count SKUs the kind that we are inseparable from.I had a drink with Scott last evening along with Ian Cutress, Paul Alcorn, and Charlie Demerjian.This is a long list. Thanks!Get the best of STH delivered weekly to your inbox. This time Intel is really in trouble.I am stunned by the GPU fabric capability.16 cores+ of maximum L2 cache, *consistency* of turbo clock of my greatest interest,Yeah, i want to see more latency figures, thats the main issue with EPYC (for my workload), they are great at alot of workloads but with workloads that rely heavily on low latency AMD is far away from beating what Intel has to offer.I’m interested in the GMI links to Vega. 2. This was in prototype system as AMD yet has to optimize it further. Here is the quick summary of what we learned today about the AMD EPYC 2 “Rome” generation: 1.
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